Programming models for next generation HPC systems

Power efficiency is fundamentally changing future processor design. We expect future CPUs to be non cache coherent hybrid chips with on-chip NUMA effects and anticipate a decrease in memory per core. This thesis evaluates existing programming models with regard to future clusters. We suggest improvements to OpenMP and OpenCL and introduce the new partitioned single assignment memory (PSAM) programming model. PSAM targets both high performance and scalability, yet tries to decrease software development complexity. To achieve these goals, PSAM relies on uncommon techniques such as dataflow-like synchronization, PGAS-like explicit data placement, and global single assignment memory, all in combination with tiling. Overall, PSAM provides efficient fine-grained pair-wise synchronization, almost purely relies on network RDMA transfers, has support for global communication algorithms and eliminates race conditions. It is possible to integrate PSAM in existing programs. We provide a prototype PSAM runtime.