Performance evaluation of parallel packet processing architectures using systemC based modeling and refinement

Network nodes, such as broadband access components, are facing new design challenges due to recent trends in applications and technologies. Stringent constraints on platform costs, performance, and power dissipation increasingly require novel programmable application-specific multi-processor architectures to be deployed. Early design space exploration is required to build a proper hardware platform. Multiple processing elements and on-chip interconnects need to be integrated. As complexity grows there is a demand to efficiently evaluate the performance of the complete system. Due to the complexity and heterogeneity it is no longer feasible to start with a model at the register-transfer level. Abstractions must be found to allow performance evaluation even in the concept phase of the design flow. A system-level performance evaluation framework is required to explore multi-processor architectures and to quantitatively evaluate different design alternatives. Due to a lack of these frameworks, today’s architectures exhibit overprovisioning of resources instead of configurability in general or reconfigurability at run-time. This leads to systems that are either designed too pessimistically in order to meet all traffic requirements or too optimistically due to inaccurate approximations of resource utilizations caused by non-deterministic real-life workload. Multi-processor architectures can address non-deterministic workload by reconfigurability that can be expressed, e. g., by load balancing. Thereby, workload is distributed among a number of processing resources. Several approaches exist to exploit load balancing of computing resources within a System-on-Chip (SoC). However, complex network nodes consist of several SoCs and their complexity prevents a quantitative evaluation of system-level load balancing at low abstractions. The above issues are concerned with two main contributions that can be summarized as follows: 1. A system-level performance evaluation framework, named SystemQ, isintroduced that provides a high abstraction, i. e. performance abstraction. SystemQ is based on queuing theory and implemented using SystemC. It therefore provides modeling at multiple abstractions and enables a refinement path between these abstractions. 2. A disciplined approach to system-level load balancing in systems consisting of several systems-on-chip is motivated. The advantages of this approach are compared quantitatively with SoC-local load balancing by using the SystemQ framework. This thesis reveals how to use the performance evaluation framework in order to efficiently model and simulate load balancing of multi-SoC platforms. The results of this work will eventually influence the design of future SoC platform architectures by means of improved performance and economical deployment of resources.