A task level programmable processor

In this thesis a multi-core platform is presented, which is programmable on a task level. Task level programming follows the idea of using techniques known from advanced microprocessors in the area of application mapping on multiple small processing elements. Register renaming and scheduling techniques for optimized and parallel execution of instructions are used for efficient execution of tasks on a multi-core system. A programming environment is developed which allows for fast implementation of applications on a multi-core system without abstaining from a sequentially executed firmware. Hence, the system does not need to be partitioned into small independent processing blocks to allow for parallel execution of the kernels. On the microarchitectural level a design template is investigated and measurement results are presented and used as estimates for the complexity analysis of a H.264 HDTV decoder in terms of power and area consumption.