On A/D converters with low-precision analog circuits and digital post-correction

Progress in the fabrication of integrated circuits (ICs) enables smaller and smaller minimum feature sizes, so that more and more transistors can be realized per chip area. Digital circuits greatly benefit from the miniaturization. By contrast, analog circuits suffer from reduced precision when component sizes are decreased, because for decreased component sizes, the respective component values increasingly deviate from their nominal values in a non-deterministic manner. Some of the resulting precision errors can be corrected by digital processing. Thus, a promising approach to mixed-signal circuit design is using small low-precision analog circuits and applying digital correction, such that the system as a whole is sufficiently precise. In this thesis, we apply the above-mentioned approach to analog-to-digital converters (ADCs), as they combine analog and digital circuits. ADCs are key building blocks of modern electronic devices which process physical quantities digitally. Examples of such devices are mobile phones, digital cameras or measurement devices such as digital voltmeters. Such devices often contain several ADCs which convert radio signals, touchscreen information, optical image data or plain voltage values into digital signals. Specifically, we consider ADCs using low-precision analog circuits and digital post-correction. We mostly consider static characteristics, ignoring dynamical issues like noise, sampling or settling. The thesis presents a few studies and ideas on the topic. We study the static accuracy of various ash-type ADCs with low-precision components and digital correction. We model the key analog components and assess the static accuracy using Monte Carlo simulations. Similarly, we extend the discussion of the static accuracy to sequential ADCs based on beta expansions (“radix < 2” conversion). We conclude that both ash-type ADCs and sequential ADCs using low-precision analog circuits are useful with proper digital correction. After fabrication, the static characteristics of the ADC's low-precision analog part are not known exactly. However, proper digital correction requires the static characteristics to be known. We thus elaborate a calibration method, which is suited for a built-in self-test (BIST). The method includes a test signal generator circuit and algorithms which estimate the static characteristics using measurement data of the test signals. The algorithms are based on Gaussian message passing on a graphical model (factor graph) of the system. In simulations, we achieve very accurate estimations of the static characteristics using the presented method. Finally, we design and manufacture an experimental pipeline ADC in a 0:13 µm CMOS process. The circuit implements the beta-expansion principle using simple analog low-precision sub-circuits.