Placement and routing of optical networks-on-chip

Optical networks-on-chip are a promising technology to improve the bandwidth of future many-core-systems. To pave the way for their practical usage, the laser power consumption of these optical systems has to be minimized. Therefore, tools for the automatic design of these optical systems are needed. Within the scope of this thesis the firrst automatic placement and routing algorithms for 3D optical Networks-on-Chip are presented. Moreover, these tools are used for a design space exploration to help the designer to determine the optimal topology, chip size, and positions of the memory controllers for his use case.